標準號：BS EN 61523-2-2002
中文標準名稱：延遲計算和功率計算標準.CMOS集成電路子程序庫.預布局延遲計算規范
英文標準名稱：Delay and power calculation standards - Pre-layout delay calculation specification for CMOS ASIC libraries
標準類型：L56
發布日期：2002/9/27 12:00:00
實施日期：2002/9/27 12:00:00
中國標準分類號：L56
國際標準分類號：31.200
適用范圍：This standard specifies the pre-layout delay calculation method for CMOS1 ASIC Libraries which contains cell based primitives and memories to be used during the pre-layout design phase of Logic simulation,Timing verfication,and Logic synthesis.The delay calculation method addressed in this standard consists of 1)Estimation of wire capacitance and 2)Delay calculation method based on tablelook-up.With use of DCL and SDF,this delay calculation method helps the user have a unified timing model for various EDA tools in the pre-layout design phase.This standard is consistent with existing standards and accepts existing standard formats,like SPEF,DCL,and SDF.Scope of this standard covers the CMOS ASIC front end timing design for using logic synthesizer,simulators,timing verifiers.The delay calculation method specified is based on the input slew rate calculation step and the port to port calculation step.During these calculation steps,the table lookup method is used.The table method of this standard specifies two interpolation methods for delay calculation.One is bi-linear interpolation which is widely used through the industry.Another is a linear interpolation using neighboring 3 points.The nature of the delay value has monotonously increasing function of convex surface.This linear interpolation has a few percent of differences between linear interpolation and SPICE result.